Multiple stage gate drive for cascode current sensing

ABSTRACT

A power converter includes an energy transfer element coupled between an input of the power converter and an output of the power converter. A control switch is coupled to a normally-on switch. The normally-on switch is coupled to the energy transfer element. A controller is coupled to control switching of the control switch to control a transfer of energy from the input of the power converter to the output of the power converter. The controller includes a drive circuit coupled to generate a drive signal in response to a control signal to control switching of the control switch. The drive signal in a first stage of a multiple stage gate drive is coupled not to fully enhance the control switch. The drive signal provided by a second stage of the multiple stage gate drive is coupled to fully enhance the control switch.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/917,432, filed on Mar. 9, 2018, which is a continuation of U.S.patent application Ser. No. 15/620,018, filed on Jun. 12, 2017, now U.S.Pat. No. 9,954,461. U.S. patent application Ser. No. 15/917,432 and U.S.Pat. No. 9,954,461 are hereby incorporated by reference.

BACKGROUND INFORMATION Field of the Disclosure

The present invention relates generally to power converters, and morespecifically, for an optimal drive which improves the current sensingfor cascode switches in power converters.

Background

Electronic devices (such as cell phones, tablets, laptops, etc.) usepower to operate. Switched mode power converters are commonly used dueto their high efficiency, small size, and low weight to power many oftoday's electronics. Conventional wall sockets provide a high voltagealternating current. In a switching power converter, a high voltagealternating current (ac) input is converted to provide a well-regulateddirect current (dc) output through an energy transfer element to a load.In operation, a switch is turned ON and OFF to provide the desiredoutput by varying the duty cycle (typically the ratio of the on time ofthe switch to the total switching period), varying the switchingfrequency, or varying the number of on/off pulses per unit time of theswitch in a switched mode power converter.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention aredescribed with reference to the following figures, wherein likereference numerals refer to like parts throughout the various viewsunless otherwise specified.

FIG. 1 is a block diagram illustrating an example power converter with acontroller and a cascode switch in accordance with the teachings of thepresent invention.

FIG. 2 is a block diagram illustrating an example current sense circuitof FIG. 1 in accordance with the teachings of the present invention.

FIG. 3 is a block diagram illustrating an example driver circuit of FIG.1 in accordance with the teachings of the present invention.

FIG. 4 is an example timing diagram illustrating one example ofwaveforms that show a control signal, a drive signal, a source signal,and a drain voltage in accordance with the teachings of the presentinvention.

FIG. 5 is an example timing diagram illustrating another example ofwaveforms that show a control signal, a drive signal, a source signal,and a drain voltage in accordance with the teachings of the presentinvention.

FIG. 6 is another example of a controller and a cascode switch inaccordance with the teachings of the present invention.

FIG. 7 is a block diagram illustrating an example current sense circuitof the example controller of FIG. 6, in accordance with the teachings ofthe present invention.

Corresponding reference characters indicate corresponding componentsthroughout the several views of the drawings. Skilled artisans willappreciate that elements in the figures are illustrated for simplicityand clarity and have not necessarily been drawn to scale. For example,the dimensions of some of the elements in the figures may be exaggeratedrelative to other elements to help to improve understanding of variousembodiments of the present invention. Also, common but well-understoodelements that are useful or necessary in a commercially feasibleembodiment are often not depicted in order to facilitate a lessobstructed view of these various embodiments of the present invention.

DETAILED DESCRIPTION

Examples of a power converter with a controller for improving the turnon of a cascode circuit with current sensing are described herein. Inthe following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Itwill be apparent, however, to one having ordinary skill in the art thatthe specific detail need not be employed to practice the presentinvention. In other instances, well-known materials or methods have notbeen described in detail in order to avoid obscuring the presentinvention.

Reference throughout this specification to “one embodiment”, “anembodiment”, “one example” or “an example” means that a particularfeature, structure or characteristic described in connection with theembodiment or example is included in at least one embodiment of thepresent invention. Thus, appearances of the phrases “in one embodiment”,“in an embodiment”, “one example” or “an example” in various placesthroughout this specification are not necessarily all referring to thesame embodiment or example. Furthermore, the particular features,structures or characteristics may be combined in any suitablecombinations and/or subcombinations in one or more embodiments orexamples. Particular features, structures or characteristics may beincluded in an integrated circuit, an electronic circuit, acombinational logic circuit, or other suitable components that providethe described functionality. In addition, it is appreciated that thefigures provided herewith are for explanation purposes to personsordinarily skilled in the art and that the drawings are not necessarilydrawn to scale.

Cascode circuits may use multiple stage gate drives in order to reduceelectromagnetic interference (EMI) associated with a switch during turnon of the switch. Current sensing of a cascode circuit may beimplemented by sensing the voltage across a low voltage switch. When thecontrol switch is not fully enhanced, the drain source resistance(RDS_(ON)) is not at a nominal value and returns inaccurate currentvalues. Associated circuitry such as overcurrent protection may notfunction properly due to inaccurate current sensing. To provide accuratecurrent sensing, the control switch must be fully enhanced in order tohave a RDS_(ON) at the nominal value. However, quickly turning ON thecontrol switch increases the EMI.

In one example, an optimal operation for the cascode circuit includes amultiple stage gate drive that turns on the switch slowly with a weakturn on drive signal to provide low EMI from the switch. After a delay,the multiple stage gate drive then fully turns on the switch with astrong turn on drive signal to provide accurate current sensing of theswitch quickly in accordance with the teachings of the presentinvention. In other words, the drive of the drive signal is initiallyweak at first during the weak turn on of the drive signal. After thedelay, the drive of the drive signal is stronger during the strong turnon of the drive signal. During the weak turn on of the drive signal, theswitch is turned on slowly, which reduces EMI. However, after the delaythe drive signal becomes a strong turn on drive signal, which quicklyturns on the switch fully, which enables accurate current sensing inaccordance with the teachings of the present invention.

To illustrate, FIG. 1 shows a functional block diagram of an examplepower converter 100 that is illustrated including an ac input voltageV_(AC) 102, a rectifier 104, a rectified voltage V_(RECT) 106, an inputcapacitor C_(IN) 108, a clamp circuit 110, an energy transfer element T1114, a primary winding 112 of the energy transfer element T1 114, asecondary winding 116 of the energy transfer element T1 114, an inputreturn 117, a rectifier D1 118, an output return 119, an outputcapacitor C1 120 coupled to a load 126, a cascode circuit 129, a sensecircuit 130, and a controller 138.

FIG. 1 further illustrates an output voltage V_(O) 124, an outputcurrent I_(O) 122, an output quantity U_(O) 128, a feedback signalU_(FB) 131, a source signal U_(S) 148 of transistor 132, a first sensefinger signal U_(C1) 149, and a second sense finger signal U_(C2) 150.

Controller 138 further includes a current sense circuit 140, a controlcircuit 142, a drive circuit 144, current sources 146 and 147, and aresistor 151.

The example switched mode power converter 100 illustrated in FIG. 1 iscoupled in a flyback configuration, which is just one example topologyof a switched mode power converter that may benefit from the teachingsof the present invention. It is appreciated that other known topologiesand configurations of switched mode power converters may also benefitfrom the teachings of the present invention. In addition, the examplepower converter shown in FIG. 1 is an isolated power converter. Itshould be appreciated that non-isolated power converters may alsobenefit from the teachings of the present invention.

The power converter 100 provides output power to the load 126 from anunregulated input voltage. In one embodiment, the input voltage is theac input voltage V_(AC) 102. In another embodiment, the input voltage isa rectified ac input voltage such as rectified voltage V_(RECT) 106. Therectifier 104 outputs rectified voltage V_(RECT) 106. In one embodiment,rectifier 104 may be a bridge rectifier. The rectifier 104 furthercouples to the energy transfer element T1 114. In some embodiments ofthe present invention, the energy transfer element T1 114 may be acoupled inductor. In other embodiments, the energy transfer element T1114 may be a transformer. In a further example, the energy transferelement T1 114 may be an inductor. In the example of FIG. 1, the energytransfer element T1 114 includes two windings, a primary winding 112 anda secondary winding 116. However, it should be appreciated that theenergy transfer element T1 114 may have more than two windings. In theexample of FIG. 1, primary winding 112 may be considered an inputwinding, and secondary winding 116 may be considered an output winding.The primary winding 112 is further coupled to a normally-on switch 132and a control switch 135, which is then further coupled to input return117.

In addition, the clamp circuit 110 is illustrated in the example of FIG.1 as being coupled across the primary winding 112 of the energy transferelement T1 114. The input capacitor C_(IN) 108 may be coupled across theprimary winding 112 and normally-on switch 132. In other words, theinput capacitor C_(IN) 108 may be coupled to the rectifier 104 and inputreturn 117.

Secondary winding 116 of the energy transfer element T1 114 is coupledto the rectifier D1 118. In the example of FIG. 1, the rectifier D1 118is exemplified as a diode. Both the output capacitor C1 120 and the load126 are shown in FIG. 1 as being coupled to the rectifier D1 118. Anoutput is provided to the load 126 and may be provided as either aregulated output voltage V_(O) 124, a regulated output current I_(O)122, or a combination of the two.

The power converter 100 further comprises circuitry to regulate theoutput, which is exemplified as output quantity U_(O) 128. In general,the output quantity U_(O) 128 is either an output voltage V_(O) 124, anoutput current I_(O) 122, or a combination of the two. A sense circuit130 is coupled to sense the output quantity U_(O) 128 and to providefeedback signal U_(FB) 131, which is representative of the outputquantity U_(O) 128. Feedback signal U_(FB) 131 may be a voltage signalor a current signal. In one example, the sense circuit 130 may sense theoutput quantity U_(O) 128 from an additional winding included in theenergy transfer element T1 114.

In another example, there may be galvanic isolation (not shown) betweenthe controller 138 and the sense circuit 130. The galvanic isolationcould be implemented by using devices such as an opto-coupler, acapacitor, or a magnetic coupling. In a further example, the sensecircuit 130 may utilize a voltage divider to sense the output quantityU_(O) 128 from the output of the power converter 100.

The cascode circuit 129 includes a normally-on switch 132 and thecontrol switch 135. In one example, the normally-on switch is a highelectron mobility transistor (HEMT). In this example, the normally-onswitch is comprised of a gallium nitride (GaN) material. In anotherexample, the normally-on switch would work similarly with a JFETcomprised of a silicon carbide (SiC) material.

The control switch 135 includes a normally-off switch 134 and a firstsense finger 136 and second sense finger 137. The gate of normally-offswitch 134 is coupled to the gate of first sense finger 136 and to thegate of second sense finger 137. To improve the accuracy of currentsensing, there is a general ratio of resistance for the first sensefinger 136 and the second sense finger 137 to the resistance RDS_(ON) ofthe normally-off switch 134.

The gate of the normally-on switch 132 is coupled such that it is OFFwhen the series normally-off switch 134 is OFF. In the example, the gateof the normally-on switch 132 is tied to the source terminal of thenormally-off switch 134, which causes the normally-on switch 132 to beturned OFF when the drain-source voltage across the normally-off switch134 results in a negative gate-source voltage for normally-off switch134 that pinches off the channel of normally-on switch 132.

Current sense circuit 140 is coupled to receive the source signal U_(S)148 of the normally-on switch 132, a first sense finger signal U_(C1)149, a second sense finger signal U_(C2) 150, and outputs a currentlimit signal U_(CL) 153 and an overcurrent signal U_(OC) 152. Controlcircuit 142 is coupled to output a control signal U_(CONT) 154 inresponse to the feedback signal U_(FB) 131, the current limit signalU_(CL) 153, the overcurrent signal U_(OC) 152.

In operation, the first sense finger signal U_(C1) 149 is generated bythe drain of sense finger 136 and the current source I_(MOD) 147. Thereference value of current source I_(MOD) 147 can be used, in anexample, for regulating the output voltage, or the ON time of thecascode circuit 129. The first sense finger 136 and second sense finger137 provides a proportional resistance in relation to the normally-offswitch 134. The second sense finger signal U_(C2) 150 is generated bythe drain of sense finger 137 and the current source I_(MAX) 146. Thereference value of current source I_(MAX) 146 is selected to representthe maximum current limit of the power converter. The additional secondsense finger in the normally-off switch 135 can improve the accuracy ofthe sense finger signal U_(C2) 150 over temperature and part variations.However, in some applications, the lower accuracy of the sense fingersignal U_(C2) 150 can be tolerated because it is used to generate thesignal which is used to provide the protection of the converter. In oneexample, the second sense finger signal U_(C2) 150 can be generated bycurrent source I_(MAX) 146 and a resistor (not shown). In some examples,the greater tolerances of the second sense finger signal U_(C2) 150 canbe tolerated using a resistor instead of using the second finger of thenormally-off switch 135 to provide a cost effective and less compleximplementation.

The drive circuit 144 is coupled to provide a drive signal U_(DR) 133 inresponse to the control signal U_(CONT) 154. The drive signal U_(DR) 133includes a multiple stage gate drive in which the first stage provides aweak turn on drive signal U_(DR) 133 to turn control switch 135 onslowly to lower the EMI, and the second stage provides a strong turn ondrive signal U_(DR) 133 after a delayed time in order to fully turn oncontrol switch 135 to provide accurate current sensing of control switch135 quickly. Further description of the drive circuit will be providedin FIG. 3.

FIG. 2 is a block diagram illustrating an example of a current sensecircuit 240, which may be an example of current sense circuit 140 ofFIG. 1, and similarly named and numbered elements referenced below maytherefore be coupled and function similar to as described above. Thecurrent sense circuit 240 is coupled to receive the source signal U_(S)248 of normally-on switch 132, the first sense finger signal U_(C1) 249,and the second sense finger signal U_(C2) 250, and outputs a currentlimit signal U_(CL) 252 and an overcurrent signal U_(OC) 251. Thecurrent sense circuit 240 includes comparators 254 and 256, and anoptional clamp circuit 257. Comparator 254 is coupled to the receive thesource signal U_(S) 248 at the non-inverting input, and the first sensefinger signal U_(C1) 249 at the inverting input, and outputs the currentlimit signal U_(CL) 252. Current limit signal U_(CL) 252 transitions toa logic high when the source signal U_(S) 248 is greater than the sensefinger signal U_(C1) 249. Comparator 256 is coupled to receive thesource signal U_(S) 248 at the non-inverting input, and the second sensefinger signal U_(C2) 250 at the inverting input. The overcurrent signalU_(OC) 251 transitions to a logic high when the source signal U_(S) 248is greater than the second sense finger signal U_(C2) 250. The clampcircuit 257 is coupled to clamp the voltage range of the source signalU_(S) 248.

FIG. 3 is a block diagram illustrating an example of a drive circuit344, which may be an example of drive circuit 144 of FIG. 1, andsimilarly named and numbered elements referenced below may therefore becoupled and function similar to as described above. Drive circuit 344 iscoupled to receive the control signal U_(CONT) 353 and output a drivesignal U_(DR) 333. The drive circuit 344 further includes transistors346, 348, and 351, and a delay circuit 349.

Transistors 346 and 351 provide a weak turn on stage, and a strong turnon stage of a multiple stage gate drive. The control signal U_(CON) 353is coupled to the gate of transistor 346, transistor 348, and the delaycircuit 349. The first stage of the multiple stage gate drive provides aweak turn on with transistor 346 for drive signal U_(DR) 333 to turn thecontrol switch on slowly to reduce the EMI. The weak turn on stageprovides a weak turn on drive signal U_(DR) 333 with transistor 346 whenthe drive signal U_(DR) 333 is at a lower value relative to the drivecircuit supply voltage (not shown). The strong turn on stage provides astrong turn on drive signal U_(DR) 333 with transistor 351 when thedrive signal U_(DR) 333 is at a value that is higher than the lowervalue and close to the drive circuit supply voltage (not shown).Transistor 346 has a higher resistance than transistor 351. The delaycircuit 349 is coupled to output a delay signal U_(DEL) 350 to delay theactivation of transistor 351 relative to the activation of transistor346 in response to the control signal U_(CON) 353. In the second stageof the multiple stage gate drive, the drive signal U_(DR) 333 has astronger turn on, which is produced by the low resistance of transistor351 to quickly enhance the control switch 135 to provide accuratecurrent sensing in accordance with the teachings of the presentinvention.

In operation, when the control signal U_(CONT) 353 transitions to alogic low, transistor 348 is turned OFF, and transistor 346 is turnedON, which provides the weak turn on for drive signal U_(DR) 333 toslowly turn on the control switch 135 to reduce EMI. The delay circuit349 is coupled to delay control signal U_(CONT) 350, and outputs adelayed control signal U_(DEL) 353. The drive signal U_(DR) 333 beginsto rise in response to the weak turn on, and charges the normally-offswitch 134, which remains turned OFF until the drive signal U_(DR) 333reaches the threshold voltage of the normally-off switch 134. When thedrive signal U_(DR) 333 reaches the threshold voltage of thenormally-off switch 134, the normally-off switch 134 starts to turn-onand the source signal begins to fall and the normally-on switch 132remains OFF because the voltage on the drain of normally-off switch 134is greater than a turn on threshold of the normally-on switch 132. Whenthe voltage on the drain of normally-off switch reaches the threshold ofthe normally-on switch 132, the normally-on switch 132 starts to turn-onand its drain voltage eventually reaches a value close to 0V when thenormally-on switch 132 is completely turned-on. However, at thatinstant, the normally-off switch 134 is not fully enhanced and itsdrain-source resistance (RDS_(ON)) is not at a nominal value. When thedelay of delay circuit 349 is over, the delayed control signal U_(DEL)353 is coupled to turn ON transistor 351, which provides the strong turnon for drive signal U_(DR) 333. The drive signal U_(DR) 333 now rises ata greater slope with the strong turn on provided by transistor 351compared to the weak turn on provided by transistor 346 of the firststage. As a result, control switch 134 is now fully enhanced, and thedrain-source resistance (RDS_(ON)) is at a nominal value, which providesaccurate current sensing in accordance with the teachings of the presentinvention.

FIG. 4 is an example timing diagram illustrating one example ofwaveforms that show a control signal, a drive signal, a source signal,and a drain voltage in accordance with the teachings of the presentinvention. In this example, the time for the control switch to becomefully enhanced (t_(FE) 457) takes longer in response to the controllernot providing a multiple stage gate drive.

Before time t0, the control signal U_(CONT) 453 is logic high, the drivesignal U_(DR) 433 is approximately zero. The source signal U_(S) 448 isat a value above the threshold value V_(TH) 455, which represents thethreshold for turning on the normally-on switch. The drain voltage V_(D)456 of the normally-on switch is a high value.

At time to, the control signal U_(CONT) 453 transitions to a logic low.The drive signal U_(DR) 443 begins to rise to the supply voltage. Thesource signal U_(S) 448 is at a value above the threshold value V_(TH)455. The drain voltage V_(D) 456 of the normally-on switch remains at alogic high.

At time t1, the source signal U_(S) 488 begins to fall but is greaterthan the threshold V_(TH) 455. The drain voltage V_(D) 456 remains thesame.

At time between t1 and t2, the source signal U_(S) 448 is falling with adownward slope.

At time t2, the drive signal U_(DR) 433 remains at nearly the same valuedue to the Miller capacitance. The source signal U_(S) 448 is at a lowervalue than it was at time t1 and reaches the voltage threshold V_(TH)455 at instant t2. The drain voltage V_(D) 456 begins to fall with adownward slope.

At time between t2 and t3, the drive signal U_(DR) 433 remains at anearly constant value due to the Miller capacitance. The source signalU_(S) 448 falls below the voltage threshold V_(TH) 455. The drainvoltage V_(D) 456 falls with a downward slope towards zero.

At time t3, the drive signal remains at the nearly same value. Thesource signal U_(S) 448 has fallen below the voltage threshold V_(TH)455, and continues to fall with a downward slope that is greater thanthe slope during time period t2 to t3. The drain voltage V_(D) 456 is atnearly zero volts.

At time t4, the drive signal begins to rise towards the supply voltageof the drive circuit. The source signal U_(S) 448 is close to zero. Thedrain voltage V_(D) 456 is close to zero volts.

At time between t4 and t5, the drive signal continues to rise. Althoughthe control switch is turned ON, the drive signal U_(DR) 433 is not highenough to fully enhance the normally-off switch and the control requiresa time between defined as the fully enhanced time T_(FE) 457, where thecontrol switch is able to provide a nominal resistance RDS_(ON).

At time t5, the drive signal U_(DR) 433 is close to the supply rail ofthe driver. The control switch is fully turned on and has a nominalresistance RDS_(ON). The source signal U_(S) 448 is at a very low valueclose to zero. The drain voltage V_(D) 456 is at zero volts and thenormally-on switch is completely turned ON.

FIG. 5 is an example timing diagram illustrating one example ofwaveforms that show a control signal, a drive signal, a source signal,and a drain voltage in accordance with the teachings of the presentinvention. In contrast to FIG. 4, the time (t_(FE) 557) for the controlswitch to be fully enhanced a provide a nominal RDS_(ON) issignificantly less than the time shown previously by using the drivecircuit described in FIG. 1 and FIG. 2.

Before time t0, the control signal U_(CONT) 553 is at logic high. Thedrive signal U_(DR) 533 is low. The delay signal U_(DEL) 550 is logichigh. The source signal U_(S) 548 is greater than the voltage thresholdV_(TH) 555, which represents the threshold for turning on thenormally-on switch. The drain voltage V_(D) 556 is representative of thedrain of the normally-on switch, which is at a high value.

At time t0, the control signal U_(CONT) 553 transitions to a logic low.The drive signal U_(DR) 533 is at a low value. The source signal U_(S)548 is greater than the voltage threshold V_(TH) 555. The drain voltageV_(D) 556 is at a high value.

At time between t0 and t1, the drive signal U_(DR) 533 rises with anupward slope towards the drive circuit supply voltage. The delay signalU_(DEL) 550 remains logic high. The source signal U_(S) 548 is at thesame value and remains greater than the voltage threshold V_(TH) 555.The drain voltage V_(D) 556 is at a high value.

At time t1, the drive signal U_(DR) 533 reaches the threshold of thecontrol switch and begins to turn on. The delay signal U_(DEL) 550remains at a logic high value. The source signal U_(S) 548 is greaterthan the voltage threshold V_(TH) 555.

At time between t1 and t2, the drive signal U_(DR) 533 remains at thethreshold value of the control switch due to the Miller capacitance, andthe control switch continues turning on. The delay signal U_(DEL) 550remains at a logic high value. The source signal U_(S) 548 begins tofall with a downward slope, but is still greater than the voltagethreshold V_(TH) 555. The drain voltage V_(D) 556 is at a high value.

At time t2, the drive signal U_(DR) 553 remains nearly at the thresholdof the control switch due to the Miller capacitance, and the controlswitch continues turning on. The delay signal U_(DEL) 550 remains at alogic high value. The source signal U_(S) 548 is approaching the voltagethreshold V_(TH) of the normally-on switch. The normally-on switchbegins to turn on once the source signal U_(S) 548 reaches the voltagethreshold V_(TH).

At time between t2 and t3, the drive signal U_(DR) 553 remains nearly atthe threshold of the control switch due to the Miller capacitance, andthe control switch continues turning on. The source signal U_(S) 548 isslightly below the voltage threshold V_(TH) 555 of the normally-onswitch and continues to turn ON.

At time t3, the drive signal U_(DR) 553 remains nearly at the thresholdof the control switch due to the Miller capacitance, and the controlswitch continues turning on. The delay signal U_(DEL) 550 remains at alogic high value. The source signal U_(S) 548 is below the voltagethreshold of the normally-on switch, and the normally-on switch iscompletely turned ON. The drain voltage V_(D) 556 is close to zero.

Between t3 and t4, the drive signal U_(DR) 553 remains nearly at thethreshold of the control switch due to the Miller capacitance, and thecontrol switch continues turning on. The delay signal U_(DEL) 550remains at a logic high value. The source signal U_(S) 548 is falling ina downward slope towards zero. The drain voltage V_(D) 556 is close tozero.

At time t4, the drive signal U_(DR) 553 remains nearly at the thresholdof the control switch due to the Miller capacitance, and the controlswitch continues turning on. The delay signal U_(DEL) 550 remains at alogic high value. The source signal U_(S) 548 is at a very low value tozero. The drain voltage V_(D) 556 is close to zero.

At time between t4 and t5 the drive signal U_(DR) 553 begins to ramptowards the voltage supply rail of the drive circuit, but the controlswitch is not fully enhanced. The RDS_(ON) of the control switchdecreases as the drive signal increases. The delay signal U_(DEL) 550remains at a logic high value. The source signal U_(S) 548 is close tozero. The drain voltage V_(D) 556 is close to zero.

At instant t5, the delay signal U_(DEL) 550 transitions to a logic low,and the second stage of the multiple stage gate drive is activated. Thesecond stage of the multiple stage drive turns on transistor 351 of FIG.3, which has a lower resistance than transistor 346. The source signalU_(S) 548 approaches zero. The drain voltage V_(D) 556 is close to zero.

At time between t5 and t6, the drive signal U_(DR) 533 ramps up towardsthe supply voltage of the drive circuit. The source signal U_(S) 548approaches zero in a negative slope. The drain voltage V_(D) is close tozero.

At time t6, the drive signal is close to the voltage of the supply railof the driver. The control switch is fully turned ON and is fullyenhanced. The time for the power switch to become fully enhanced (t_(FE)557) is less than the time to be fully enhanced as shown in FIG. 4.

FIG. 6 is another example of a controller for sensing a current ofcascode switch in accordance with the teachings of the presentinvention. The cascode switch includes a control switch 635 and anormally-on switch 632.

The control switch 635 includes a normally-off switch 634 and a firstsense finger 636.

The controller 638 is coupled to receive the source signal U_(S) 648,first sense finger signal U_(C1) 649, feedback signal U_(FB) 631, andoutputs a drive signal U_(DR) 633 to the control switch 635. Controller638 further includes a current sense circuit 640, a control circuit 642,and a drive circuit 644.

Current sense circuit 640 is coupled to receive the source signal U_(S)648 of the normally-on switch 632, the first sense finger signal U_(C1)649, a second sense finger signal U_(C2) 650, and outputs a currentlimit signal U_(CL) 653 and an overcurrent signal U_(OC) 652.

Control circuit 642 is coupled to receive the feedback signal U_(FB)631, the current limit signal U_(CL) 653, an overcurrent signal U_(OC)652, and outputs a control signal U_(CONT) 654.

In operation, the first sense finger signal U_(C1) 649 is generated bythe drain of first sense finger 636 and the current source I_(M)OD 647.The value of current source I_(M)OD 647 is selected for regulating theoutput voltage, or the ON time of the cascode circuit. First sensefinger 636 provides a proportional resistance to the switch 634. Thesecond sense finger signal U_(C2) 650 is generated by the current sourceI_(MAX) 646 and the resistor 651. The reference value of current sourceI_(MAX) 646 is selected to represent the maximum current limit of thepower converter.

The drive circuit 644 is coupled to provide a drive signal U_(DR) 633 inresponse to the control signal U_(CONT) 654. The drive signal U_(DR) 633includes a multiple stage gate drive in which the first stage is a weakturn on to lower the EMI, and the second stage is a strong turn on aftera delayed time in order to provide accurate current sensing inaccordance with the teachings of the present invention.

FIG. 7 is a block diagram illustrating one example of a current sensecircuit 740, which may be an example of current sense circuit 140 ofFIG. 1, or 640 of FIG. 6, and similarly named and numbered elementsreferenced below may therefore be coupled and function similar to asdescribed above. The current sense circuit 740 is coupled to receive thesource signal U_(S) 748, the first sense finger signal U_(C1) 749, andthe second sense finger signal U_(C2) 750, and outputs a current limitsignal U_(CL) 752 and an overcurrent signal U_(OC) 751. The currentsense circuit 740 includes comparators 754 and 756, and an optionalclamp circuit 757. Comparator 754 is coupled to the receive the sourcesignal U_(S) 748, which in one example may be received through optionalclamp circuit 757, at the non-inverting input, and the sense fingersignal U_(C1) 749 at the inverting input, and outputs the current limitsignal U_(CL) 752. Current limit signal U_(CL) 752 transitions to alogic high when the source signal U_(S) 748 is greater than the sensefinger signal U_(C1) 749. Comparator 756 is coupled to receive thesource signal U_(S) 248, which in one example may be received throughoptional clamp circuit 757, at the non-inverting input, and the secondsense finger signal U_(C2) 750 at the inverting input. The overcurrentsignal U_(OC) 751 transitions to a logic high when the source signalU_(S) 748 is greater than the second sense finger signal U_(C2) 750.

The above description of illustrated examples of the present invention,including what is described in the Abstract, are not intended to beexhaustive or to be limitation to the precise forms disclosed. Whilespecific embodiments of, and examples for, the invention are describedherein for illustrative purposes, various equivalent modifications arepossible without departing from the broader spirit and scope of thepresent invention. Indeed, it is appreciated that the specific examplevoltages, currents, frequencies, power range values, times, etc., areprovided for explanation purposes and that other values may also beemployed in other embodiments and examples in accordance with theteachings of the present invention.

These modifications can be made to examples of the invention in light ofthe above detailed description. The terms used in the following claimsshould not be construed to limit the invention to the specificembodiments disclosed in the specification and the claims. Rather, thescope is to be determined entirely by the following claims, which are tobe construed in accordance with established doctrines of claiminterpretation. The present specification and figures are accordingly tobe regarded as illustrative rather than restrictive.

What is claimed is:
 1. A power converter, comprising; an energy transferelement coupled between an input of the power converter and an output ofthe power converter; a control switch coupled to a normally-on switch,the normally-on switch further coupled to the energy transfer element;and a controller configured to control switching of the control switch,the control switch configured to control a transfer of energy from theinput of the power converter to the output of the power converter,wherein the controller comprises: a drive circuit configured to generatea drive signal in response to a control signal to control switching ofthe control switch, wherein the drive signal in a first stage of amultiple stage gate drive is configured not to fully enhance the controlswitch, and wherein the drive signal provided by a second stage of themultiple stage gate drive is configured to fully enhance the controlswitch.
 2. The power converter of claim 1, wherein the control switchcomprises one or more sense fingers coupled to the control switch,wherein the one or more sense fingers has a general ratio of resistanceto a resistance of the normally-on switch.
 3. The power converter ofclaim 2, wherein the controller further comprises: a current sensecircuit configured to generate a current limit signal and an overcurrentsignal in response to a source signal and one or more sense fingersignals from the control switch; and a control circuit configured togenerate the control signal in response to the current limit signal andthe overcurrent signal.
 4. The power converter of claim 3, wherein theone or more sense finger signals is generated by a drain of the one ormore sense fingers coupled to a current source.
 5. The power converterof claim 4, wherein a value of the current source is representative ofregulating an output voltage or an ON time of the power converter. 6.The power converter of claim 4, wherein a value of the current source isrepresentative of a maximum current limit of the power converter.
 7. Thepower converter of claim 1, the drive circuit comprising: a firsttransistor with a first resistance configured to receive the controlsignal, the first transistor further configured to generate the drivesignal of the first stage of the multiple stage gate drive; a delaycircuit configured to receive the control signal, the delay circuitfurther configured to output a delayed control signal; and a secondtransistor with a second resistance configured to receive the delayedcontrol signal, the second transistor further configured to generate thedrive signal in the second stage of the multiple stage gate drive,wherein the first resistance of the first transistor is greater than thesecond resistance of the second transistor.
 8. The power converter ofclaim 1, wherein the normally-on switch is a high electron mobilitytransistor.
 9. The power converter of claim 1, wherein the normally-onswitch is comprised of gallium nitride material (GaN).
 10. The powerconverter of claim 1, wherein the normally-on switch is a JFET comprisedof a silicon carbide (SiC) material.
 11. A controller for use in a powerconverter, comprising: a current sense circuit configured to generate acurrent limit signal and an overcurrent signal in response to a sourcesignal, a first sense finger signal, and a second sense finger signal; acontrol circuit configured to generate a control signal in response tothe current limit signal and the overcurrent signal; and a drive circuitconfigured to generate a drive signal for a cascode circuit with amultiple stage gate drive in response to the control signal, wherein thedrive signal in a first stage of the multiple stage gate drive is a weakturn on drive signal configured to turn the cascode circuit on slowly toreduce electromagnetic interference (EMI), and wherein the drive signalin a second stage of the multiple stage gate drive is a strong turn ondrive signal configured to fully turn on the cascode circuit quickly toenable accurate current sensing of the cascode circuit.
 12. Thecontroller of claim 11, wherein the cascode circuit comprises a lowvoltage switch coupled to a normally-on switch.
 13. The controller ofclaim 12, wherein the drive signal provided by the first stage of themultiple stage gate drive is configured not to fully enhance the lowvoltage switch to reduce the electromagnetic interference (EMI) of thecascode circuit.
 14. The controller of claim 13, wherein the drivesignal provided by the first stage of the multiple stage gate drive isconfigured to provide a weak turn on of the low voltage switch.
 15. Thecontroller of claim 13, wherein the drive signal provided by the secondstage of the multiple stage gate drive is configured to fully enhancethe low voltage switch to enable the cascode circuit to increaseaccuracy of current sensing.
 16. The controller of claim 14, wherein thedrive signal provided by the second stage of the multiple stage gatedrive is configured to provide a strong turn on of the low voltageswitch.
 17. The controller of claim 15, the low voltage switch of thecascode circuit further comprising a first sense finger coupled to thelow voltage switch, wherein a gate of the first sense finger is coupledto a gate of the low voltage switch.
 18. The controller of claim 17, thelow voltage switch further comprising a second sense finger coupled tothe low voltage switch, wherein a gate of the second sense finger iscoupled to the gate of the low voltage switch.
 19. The controller ofclaim 12, wherein the normally-on switch is comprised of gallium nitride(GaN) material.
 20. The controller of claim 17, wherein the first sensefinger signal is generated by a first current source coupled to a drainof the first sense finger.
 21. The controller of claim 18, wherein thesecond sense finger signal is generated by a second current sourcecoupled to a drain of the second sense finger.
 22. The controller ofclaim 12, wherein the normally-on switch is comprised of silicon carbide(SiC) material.